Last Updated on December 14, 2024
After learning about logic gates, next step is to know and learn about Flip-Flops, these are the fundamental building blocks in digital electronics. Flip-Flop can give bistable output and store a single bit of data. So that Flip-Flops are used in applications like memory, Data transfer, counter, synchronizer etc..,
In simple way you can say that Flip-Flop is a tiny digital switch which can remember its position. Output of Flip-Flop will have two stage positions called states, that is logic HIGH (1) and logic LOW (0). It is controlled by input signals and clock pulse. Flip Flop only changes state at specific intervals. Due to its character Flip Flops are evolved as a crucial element in modern electronics.
Types of Flip-Flop
Here is the list of basic Flip-Flops used in digital electronics and applications, before that remember one thing Flip-Flops without a Clock signal are typically referred to as Latches. You may know that latches are Asynchronous combinational circuit that changes their output state immediately when their input changes without needing a clock pulse.
- SR Flip Flop
- D Flip Flop
- JK Flip Flop
- T Flip Flop
These are the four basic Flip-Flops used in digital electronics (you can cascade it like master slave to do task). NAND and NOR gates are used to design Flip-Flop, depends on the requirement we can make it as Active LOW or Active HIGH.
SR Flip Flop
It can be termed as Set-Reset flip flop. It is the simplest type of Flip-Flop. It will have two Inputs S (Set) and R (Reset) and then two outputs Q and Ǭ.
SR Flip Flop Truth Table
| CLK | S (Set) | R (Reset) | Q (Next State) | Q̅ (Complement) | Comments |
|---|---|---|---|---|---|
| 0 | X | X | Q (Previous State) | Q̅ | No change (Hold State) |
| 1 | 0 | 0 | Q (Previous State) | Q̅ | No change (Hold State) |
| 1 | 0 | 1 | 0 | 1 | Reset state |
| 1 | 1 | 0 | 1 | 0 | Set state |
| 1 | 1 | 1 | Invalid | Invalid | Not allowed (Indeterminate) |
When the CLK (Clock) pulse is low (0), the flip flop ignores the input s and R and the output holds their previous state (Q and Q̅). During CLK is High (1) and Inputs S = 1 and R = 0 then the output Q is set to 1 (Set Condition), If S = 0 and R = 1 then the output Q is Reset to 0 ( Reset Condition). Look at the truth table for other conditions.
D Flip Flop
D Flip Flop have single Data input (D) and Clock input CLK. Output Q follows the Input (D) at the rising edge or falling edge of the clock pulse. So that it eliminates the undefined state of SR Flip Flop. This D Flip Flop widely used in counters, shift registers and other sequential circuits.
D Flip Flop Truth Table
| CLK | D (Data) | Q (Next State) | Q̅ (Complement) | Comments |
|---|---|---|---|---|
| ↓ (Falling) | X | Q (Previous State) | Q̅ | No change (Hold State) |
| ↑ (Rising) | 0 | 0 | 1 | Reset state (Q = 0) |
| ↑ (Rising) | 1 | 1 | 0 | Set state (Q = 1) |
The data is captured at the ↑ (Rising) edge of the clock signal and gives output state.
JK Flip Flop
JK Flip Flop used to storing and flipping binary data (0 and1). It have two inputs J and K, then two outputs Q and Q̅. Output of the JK flip flop is depends on the combination of inputs.
JK Flip Flop Truth Table
| CLK | J | K | Q (Next State) | Q̅ (Complement) | Comments |
|---|---|---|---|---|---|
| ↓ (Falling) | X | X | Q (Previous State) | Q̅ | No change (Hold State) |
| ↑ (Rising) | 0 | 0 | Q (Previous State) | Q̅ | No change (Hold State) |
| ↑ (Rising) | 0 | 1 | 0 | 1 | Reset state |
| ↑ (Rising) | 1 | 0 | 1 | 0 | Set state |
| ↑ (Rising) | 1 | 1 | Q̅ (Toggle) | Q (Toggle) | Toggle state |
During the CLK = 0 JK flip flop ignores the inputs, During the CLK = 1 JK flip flop changes its state, all the following conditions are under CLK = 1 or rising, If both inputs are 0, then the output Q stays same as before state. If J = 1 and K = 0 then the output becomes High (Q = 1 Set State). If J = 0 and K = 1 then the output becomes Low (Q = 0 Reset state). If both inputs are 1 then the output ‘flips’ that is toggle between 0 and 1.
T Flip Flop
This T Flip Flop toggles its state on every Clock pulse during the input T = 1. This is also behaves like JK Flip Flop. But with single input, it can be termed as Toggle Flip Flop.
T Flip Flop Truth Table
| CLK | T (Toggle) | Q (Next State) | Q̅ (Complement) | Comments |
|---|---|---|---|---|
| ↓ (Falling) | X | Q (Previous State) | Q̅ | No change (Hold State) |
| ↑ (Rising) | 0 | Q (Previous State) | Q̅ | No change (Hold State) |
| ↑ (Rising) | 1 | Q̅ (Toggle) | Q (Toggle) | Toggle state |
During the Falling Edge of Clock this flip flop ignores the input T. During the Rising Edge of Clock, If the input T = 0 then there is no change in the output. If T = 1 then the output toggles that is switch to the opposite state.